In logic verification of a hardware design, test patterns are prepared by changing combinations of values assigned to parameters as input to be verified. Conventionally, combinations of values to be tested are changed depending on the existence or absence of a relation between parameters. In general, parameters related to each other are tested in more combinations as compared to parameters not related with each other. In addition, related parameters are extracted from a specification for each function, a strength of the relation between the parameters is determined from the behavior of the function (such as an algorithm), and combinations are changed based on the determined strength of the relation.
Various logic verification tools have been conventionally disclosed for preparation of test patterns, such as a method by which correlation between primary input is provided as a constraint condition and an input pattern is prepared so as to satisfy the condition, and a method by which validity of a simulation result is determined (for example, refer to Japanese Laid-Open Patent Application Publication Nos. H07-35828 and H07-49887).
However, such conventional logic verification has a drawback in that a boundary condition of a parameter differs between the specification and implementation. In addition, conventional logic verification may falsely indicate parameters with no relation in a specification to have a relation in implementation, and conversely, may indicate parameters with a relation in the specification to have no relation in implementation. Further, conventional logic verification has a huge problem in that a specification and implementation differ in a sequence of calculation (e.g. sharing of an operator, or changing of a sequence) due to temporal and areal constraints on the implementation, thereby increasing the possibility of missing points to be tested.
Conventionally, these failures are overlooked, and thus combinations of values assigned to parameters as input to be verified, are not sufficiently selected, and validity of the combinations themselves are not clear. Accordingly, it is not possible to perform logic verification completely covering signal changes in verification targets and the performance of functions realized by the verification targets, leading to decreased reliability of the logic verification.